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| ST24LC21 1Kb (x8) DUAL MODE SERIAL EEPROM for VESA Plug&Play NOT FOR NEW DESIGN 1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION 2.5V to 5.5V SINGLE SUPPLY VOLTAGE 400k Hz COMPATIBILITY OVER the FULL RANGE of SUPPLY VOLTAGE TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE PAGE WRITE (up to 8 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCES ST24LC21 is replaced by the ST24LC21B 8 1 PSDIP8 (B) 0.25mm Frame 8 1 SO8 (M) Figure 1. Logic Diagram DESCRIPTION The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits.This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The ST24LC21 cannot switch from the I2C bidirectional mode to the Transmit Only mode (except when the power supply is removed). The device operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. VCC SCL ST24LC21 VCLK SDA Table 1. Signal Names SDA SCL VCC VSS VCLK Serial Data Address Input/Output Serial Clock (I C mode) Supply Voltage Ground Clock Transmit only mode 2 VSS AI01489 June 1997 This is information on a product still in production but not recommended for new designs. 1/18 ST24LC21 Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections ST24LC21 NC NC NC VSS 1 2 3 4 8 7 6 5 AI01499 ST24LC21 VCC VCLK SCL SDA NC NC NC VSS 1 2 3 4 8 7 6 5 AI01500 VCC VCLK SCL SDA Warning: NC = Not Connected Warning: NC = Not Connected Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature, Soldering Input or Output Voltages Supply Voltage Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model) (3) (2) Value grade 1 0 to 70 -65 to 150 Unit C C C V V V V (SO8 package) (PSDIP8 package) 40 sec 10 sec 215 260 -0.3 to 6.5 -0.3 to 6.5 4000 500 Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500 ). 3. EIAJ IC-121 (Condition C) (200pF, 0 ). Table 3. Device Select Code Device Code Bit Device Select b7 1 b6 0 b5 1 b4 0 b3 X Chip Enable b2 X b1 X RW b0 RW Note: The MSB b7 is sent first. X = 0 or 1. 2/18 ST24LC21 Figure 3. Transmit Only Mode Waveforms VCC SCL SDA tVPU VCLK 1 2 8 9 10 Bit 7 Bit 6 11 VCC SCL SDA Bit 6 Bit 5 Bit 4 Bit 0 Bit 7 Bit 6 VCLK 12 13 17 18 19 20 AI01501 Table 4. Operating Modes Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write Note: X = VIH or VIL RW bit '1' '0' '1' '1' '0' '0' VCLK X X X X VIH VIH Bytes 1 1 1 to 128 1 8 Initial Sequence START, Device Select, RW = '1' START, Device Select, RW = '0', Address, reSTART, Device Select, RW = '1' Similar to Current or Random Mode START, Device Select, RW = '0' START, Device Select, RW = '0' 3/18 ST24LC21 Figure 4. Transition Mode Waveforms Transmit Only Mode SCL Bi-Directional Mode SDA VCLK AI01502 Transmit Only Mode After a Power-up, the device is in the Transmit Only mode. A proper initialization sequence must supply nine clock pulses on the VCLK pin (in order to internally synchronize the device). During this initialization sequence, the SDA pin is in high impedance. On the rising edge of the tenth pulse applied on VCLK pin, the device will output the first bit of byte located at address 00h (most significant bit first). A byte is clocked out (on SDA pin) with nine clock pulses on VCLK: 8 clock pulses for the data byte and one extra clock pulse for a Don't Care bit. As long as the SCL pin is held high, each byte of the memory array is transmitted serially on the SDA pin with an automatic address increment. When the last byte is transmitted, the address counter will roll-over to location 00h. I2C Bidirectional Mode The device can be switched from Transmit Only mode to I2C Bidirectional mode by applying a valid high to low transition on the SCL pin (see Figure 4). When the device is in the I2C Bidirectional mode, the VCLK input enables (or inhibits) the execution of any write instruction: if VCLK = 1, write instructions are executed; if VCLK = 0, write instructions are not executed. The device is compatible with the I2C standard, two wire serial interface which uses a bi-directional data bus and serial clock. The device carries a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. The device behaves as a slave device in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits (identification code 1010XXX), plus one read/write bit and terminated by an acknowledge bit. When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. 4/18 ST24LC21 SIGNAL DESCRIPTIONS I2C Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 5). Transmit Only Clock (VCLK). The VCLK input pin is used to synchronize data out when the ST24LC21 is in Transmit Only mode. The VCLK input offers also a Write Enable (active high) function when the ST24LC21 is in I2C bidirectional mode. Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as pull up (see Figure 5). DEVICE OPERATION I2C Bus Background The ST24LC21 supports the I2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The ST24LC21 are always slave devices in all communications. Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24LC21 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given. Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the ST24LC21 and the bus master. A STOP condition at the end of a Read command forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successfull data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. Figure 5. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF) AI01665 RL SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS CBUS 1000 5/18 ST24LC21 Table 5. Input Parameters (1) (TA = 25 C, f = 100 kHz ) Symbol CIN CIN tLP Parameter Input Capacitance (SDA) Input Capacitance (other pins) Low-pass filter input time constant (SDA and SCL) Test Condition Min Max 8 6 300 Unit pF pF ns Note: 1. Sampled only, not 100% tested. Table 6. DC Characteristics (TA = 0 to 70 C; VCC = 2.5V to 5.5V) Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current Test Condition 0V VIN VCC 0V VOUT VCC SDA in Hi-Z VCC = 5V, fC = 400kHz (Rise/Fall time < 10ns) VCC = 2.5V, fC = 400kHz VIN = VSS or VCC, VCC = 5V VIN = VSS or VCC, VCC = 5V, fC = 400kHz Supply Current (Standby) VIN = VSS or VCC, VCC = 2.5V VIN = VSS or VCC, VCC = 2.5V, fC = 400kHz VIL VIH VIL VIH VOL Input Low Voltage (SCL, SDA) Input High Voltage (SCL, SDA) Input Low Voltage (VCLK) Input High Voltage (VCLK) Output Low Voltage IOL = 3mA IOL = 6mA, VCC = 5V 2.5V VCC 4V VCC > 4V -0.3 0.7 VCC -0.3 -0.3 2 Min Max 2 2 2 1 100 300 5 50 0.3 VCC VCC + 1 0.2 VCC 0.8 VCC + 1 0.4 0.6 Unit A A mA mA A A A A V V V V V V V ICC ICC1 Supply Current (Standby) ICC2 6/18 ST24LC21 Table 7. AC Characteristics, I2C Bidirectional Mode for Clock Frequency = 400kHz (TA = 0 to 70 C; VCC = 2.5V to 5.5V) Symbol tCH1CH2 tCL1CL2 tDH1DH2 tDL1DL2 (1) (1) (1) (1) Alt tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Parameter Min Max 300 300 Unit ns ns ns ns ns ns ns s s ns ns s 20 20 600 600 600 0 1.3 100 600 1.3 200 200 300 300 tCHDX (2) tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV tCLQX fC tW Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Data Out Valid Clock Low to Data Out Transition Clock Frequency Write Time 900 ns ns 400 10 kHz ms Notes: 1. Sampled only, not 100% tested. 2. For a reSTART condition, or following a write cycle. Data Input. During data input the ST24LC21 sample the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. Memory Addressing. To start communication between the bus master and the slave ST24LC21, the master must initiate a START condition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the device select code (7 bits) and a READ or WRITE bit. The 4 most significant bits of the device select code are the device type identifier, corresponding to the I2C bus definition. For these memories the 4 bits are fixed as 1010b. The following 3 bits are Don't Care. The 8th bit sent is the read or write bit (RW), this bit is set to '1' for read and '0' for write operations. If a match is found, the corresponding memory will acknowledge the identification on the SDA bus during the 9th bit time. Write Operations Following a START condition the master sends a device select code with the RW bit reset to '0'. The memory acknowledges this and waits for a byte address. After receipt of the byte address the device again responds with an acknowledge. In I2C bidirectional mode, any write command with VCLK = 0 will not modify data and will be acknowledged on data bytes, as shown in Figure 11. Byte Write. In the Byte Write mode the master sends one data byte, which is acknowledged by the memory. The master then terminates the transfer by generating a STOP condition. Page Write. The Page Write mode allows up to 8 bytes to be written in a single write cycle, provided that they are all located in the same 'row' in the memory: that is the most significant memory address bits are the same. The master sends from one up to 8 bytes of data, which are each acknowledged by the memory. 7/18 ST24LC21 Table 8. AC Characteristics, I2C Bidirectional Mode for Clock Frequency = 100kHz (TA = 0 to 70 C; VCC = 2.5V to 5.5V) Symbol tCH1CH2 tCL1CL2 tDH1DH2 tDL1DL1 tCHDX (1) Alt tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR Clock Rise Time Clock Fall Time Input Rise Time Input Fall Time Parameter Min Max 1 300 1 300 Unit s ns s ns s s s s s ns s s Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Next Data Out Valid Data Out Hold Time Clock Frequency Write Time 4.7 4 4 0 4.7 250 4.7 4.7 0.3 300 100 10 3.5 tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV (2) s ns kHz ms tCLQX fC tW Notes: 1. For a reSTART condition, or following a write cycle. 2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP conditions. Table 9. AC Characteristics, Transmit-only Mode (TA = 0 to 70 C; VCC = 2.5V to 5.5V) Symbol tVCHQX tVCHVCL tVCLVCH tCLQZ tVPU (1,2) (2) (2) Alt tVAA tVHIGH tVLOW tVHZ Parameter Output Valid from VCLK VCLK High Time VCLK Low Time Mode Tansition Time Transmit-only Power-up Time Min Max 500 Unit ns ns s 600 1.3 500 0 1 1 ns ns s s tVH1VH2 tVL1VL2 tR tF VCLK Rise Time VCLK Fall Time Notes: 1. Refer to Figure 3. 2. Sampled only, not 100% tested. 8/18 ST24LC21 Figure 6. AC Waveforms tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE tCLCH tDXCX tCHDH tDHDL STOP & BUS FREE SCL tCLQV SDA OUT DATA VALID tCLQX DATA OUTPUT tDHDL SCL tW SDA IN tCHDH STOP CONDITION WRITE CYCLE tCHDX START CONDITION tVCHVCL VCLK tVCHQX SDA tVCLVCH tCLQZ SCL AI01503 9/18 ST24LC21 AC MEASUREMENT CONDITIONS Input Rise and Fall Times Input Pulse Voltages SDA, SCL Input Pulse Voltages VCLK 50ns 0.2VCC to 0.8VCC 0.4V to 2V 0.2VCC 0.8VCC 0.7VCC 0.3VCC AI00825 Figure 7. AC Testing Input Output Waveforms Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC Figure 8. I2C Bus Protocol SCL SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION SCL 1 2 3 7 8 9 SDA MSB ACK START CONDITION SCL 1 2 3 7 8 9 SDA MSB ACK STOP CONDITION AI00792 10/18 ST24LC21 Figure 9. Write Cycle Polling using ACK WRITE Cycle in Progress START Condition DEVICE SELECT with RW = 0 NO First byte of instruction with RW = 0 already decoded by ST24xxx ACK Returned YES NO Next Operation is Addressing the Memory YES ReSTART Send Byte Address STOP Proceed WRITE Operation Proceed Random Address READ Operation AI01099B DEVICE OPERATIONS (cont'd) After each byte is transfered, the internal byte address counter (3 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter 'roll-over' which could result in data being overwritten. Note that, for any write mode, the generation by the master of the STOP condition starts the internal memory program cycle. All inputs are disabled until the completion of this cycle and the memory will not respond to any request. Minimizing System Delays by Polling On ACK. During the internal write cycle, the memory disconnects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (tW) is given in the AC Characteristics table, since the typical time is shorter, the time seen by the system may be reduced by an ACK polling sequence issued by the master. The sequence is as follows: - Initial condition: a Write is in progress (see Figure 9). - Step 1: the Master issues a START condition followed by a Device Select byte (1st byte of the new instruction). - Step 2: if the memory is busy with the internal write cycle, no ACK will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it will respond with an ACK, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction was already sent during Step 1). 11/18 ST24LC21 Figure 10. Write Modes Sequence VCLK ACK BYTE WRITE DEV SEL ACK DATA IN ACK BYTE ADDR R/W START VCLK ACK PAGE WRITE DEV SEL ACK DATA IN 1 ACK DATA IN 2 BYTE ADDR R/W ACK DATA IN N START ACK STOP STOP AI01504B Read Operations On delivery, the memory content is set at all "1's" (or FFh). Current Address Read. The memory has an internal byte address counter. Each time a byte is read, this counter is incremented. For the Current Address Read mode, following a START condition, the master sends a memory address with the RW bit set to '1'. The memory acknowledges this and outputs the byte addressed by the internal byte address counter. This counter is then incremented. The master does NOT acknowledge the byte out- put, but terminates the transfer with a STOP condition. Random Address Read. A dummy write is performed to load the address into the address counter, see Figure 12. This is followed by another START condition from the master and the byte address is repeated with the RW bit set to '1'. The memory acknowledges this and outputs the byte addressed. The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition. 12/18 ST24LC21 Figure 11. Inhibited Write when VCLK = 0 VCLK CONTROL BYTE ACK WORD ADDR DATA ACK BYTE WRITE START ACK CONTROL BYTE ACK WORD ADD n DATA n ACK DATA n + 1 STOP ACK DATA n + 7 ACK PAGE WRITE START ACK STOP AI01505 Sequential Read. This mode can be initiated with either a Current Address Read or a Random Address Read. However, in this case the master DOES acknowledge the data byte output and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must NOT acknowledge the last byte output, but MUST generate a STOP condition. The output data is from consecutive byte addresses, with the internal byte address counter automat- ically incremented after each byte output. After a count of the last memory address, the address counter will 'roll- over' and the memory will continue to output data. Acknowledge in Read Mode. In all read modes the ST24LC21 wait for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the ST24LC21 terminate the data transfer and switches to a standby state. 13/18 ST24LC21 Figure 12. Read Modes Sequence ACK CURRENT ADDRESS READ DEV SEL NO ACK DATA OUT START R/W ACK RANDOM ADDRESS READ DEV SEL * ACK DEV SEL * STOP ACK NO ACK DATA OUT BYTE ADDR START R/W START R/W ACK SEQUENTIAL CURRENT READ DEV SEL ACK ACK NO ACK DATA OUT 1 R/W DATA OUT N START ACK SEQUENTIAL RANDOM READ DEV SEL * ACK DEV SEL * ACK ACK BYTE ADDR DATA OUT 1 START R/W START R/W ACK NO ACK DATA OUT N STOP AI00794C Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical. 14/18 STOP STOP ST24LC21 ORDERING INFORMATION SCHEME Example: ST24LC21 M 1 TR Package B M PSDIP8 0.25mm Frame SO8 Temperature Range 1 0 to 70 C Option TR Tape & Reel Packing Devices are shipped from the factory with the memory content set at all "1's" (FFh). For a list of available options (Package, etc...) or for further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. 15/18 ST24LC21 PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame Symb Typ A A1 A2 B B1 C D E E1 e1 eA eB L N PSDIP8 mm Min 3.90 0.49 3.30 0.36 1.15 0.20 9.20 7.62 - 6.00 2.54 - 7.80 Max 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.00 8 3.80 0.100 0.300 Typ inches Min 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.118 8 0.150 A2 A1 B B1 D N A L eA eB C e1 E1 1 E PSDIP-a Drawing is not to scale 16/18 ST24LC21 SO8 - 8 lead Plastic Small Outline, 150 mils body width Symb Typ A A1 B C D E e H h L N CP SO8 mm Min 1.35 0.10 0.33 0.19 4.80 3.80 1.27 - 5.80 0.25 0.40 0 8 0.10 Max 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ inches Min 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 h x 45 A C B e D CP N E 1 H A1 L SO-a Drawing is not to scale 17/18 ST24LC21 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1997 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 18/18 |
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